By M.C. Bhuvaneswari
This publication describes how evolutionary algorithms (EA), together with genetic algorithms (GA) and particle swarm optimization (PSO) can be used for fixing multi-objective optimization difficulties within the zone of embedded and VLSI procedure layout. Many advanced engineering optimization difficulties might be modelled as multi-objective formulations. This publication presents an advent to multi-objective optimization utilizing meta-heuristic algorithms, GA and PSO and the way they are often utilized to difficulties like hardware/software partitioning in embedded structures, circuit partitioning in VLSI, layout of operational amplifiers in analog VLSI, layout house exploration in high-level synthesis, hold up fault trying out in VLSI trying out and scheduling in heterogeneous disbursed structures. it truly is proven how, in each one case, many of the facets of the EA, particularly its illustration and operators like crossover, mutation, and so on, will be individually formulated to resolve those difficulties. This booklet is meant for layout engineers and researchers within the box of VLSI and embedded method layout. The publication introduces the multi-objective GA and PSO in an easy and simply comprehensible means that would entice introductory readers.
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Extra info for Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems
GD takes a small value for good convergence and Δ takes a small value for good diversity-preserving algorithm. The algorithm with an overall small value of W means that the algorithm is efficient in both the aspects. To combine the two metrics, the weights A and B are chosen depending on the importance of the performance metric. 5. The performance metrics namely ER, GD, MFE can be determined only when the true pareto-optimal solutions are known for the specified problem. The other metrics S, Δ, and W can be determined even when the true pareto-optimal solutions are unknown.
An achievement of fast, low-power, and low-area integrated circuits is the major requirement in the electronic industry. The Operational Amplifier (OpAmp) is the most versatile and widely used building blocks in analog electronics. The CMOS OpAmp design problem is a complex and tedious task, which requires many compromises to be made between conflicting objectives. The performance of an OpAmp is characterized by number of parameters, such as, gain, power, slew rate, and area. These performance parameters are determined by transistor dimensions, bias current, and compensation capacitance values.
The HW implementation of each task is associated with an HW area and an HW time. The HW area (CH) represents the area occupied by the task while implementing in HW and the HW time (tH) is the execution time of the task if implemented in HW. If one of the two communicating tasks is implemented in HW, and the other in SW processor, then the communication cost (CC) between them incurs a significant overhead and is considered during partitioning. If the two tasks are both in HW or both in SW, then the overhead is much lower and the communication cost is neglected.
Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems by M.C. Bhuvaneswari